Some technical details

The Diode ROM consists of four bit matrices, a 3D-printed "book-like" case, a data cable and an UNIBUS resp. QBUS controller.

Bit-matrix board

The 1024 bits are distributed onto 4 four diode matrices with 256 bits each, organized as 16 data rows and 16 bit columns (as the PDP-11 is a 16 bit machine).

bit matrix

This gives a total of 64 PDP-11 words, with an octal address range from <base-address>+000 to <base-address>+176

Vertically data rows are labeled with minor digits of their word address, horizontal data bits are grouped into 1-3-3-3-3 fields, to make binary-to-octal conversion easier.

 Every diode has an "enable" jumper, which removes it from the matrix when pulled. An existing jumper is a logic "one", a removed jumper is a "zero".
I experimented with minature switches first, see below. The jumpers are slower to set, but make good contact, give a clearer impression of the bit patterns and even can be color coded.

For each data row and bit columns there exists an "Activity LED", a total of 16+16 = 32.
The last data access is indicated by a single row LED, and all "one" bits of the access data words.
These are en excat duplicate of the bit jumpers.

All PCBs share a common 34 wire flat cable to PDP-11 controller.
So each PCB has a local page address jumper, to number it uniquely 0..3.

Book case

A 3D printed "book-like" case contains all four bit matrices. Mounting frames hold the PCBs.

book case

The overall geometry was surprisingly complex to calculate, but now you can "flip" through the pages like in a real book.

book into pages


PDP-11 controller board

A UNIBUS resp. QBUS controller board interfaces to PDP-11.
The ROM matrix is accessed by regular DATI bus cycle and works like any other peripheral.
The 64 word ROM range (octal size 200) can be selected to occur anywhere in the PDP-11 IO-Page, the upper 8K of the address range.
For 16/18/22-bits PDP-11s the octal base address is therefore 160000/760000/17760000 .

The on-board logic is made from separate 74xx TTL chips, historically correct. (Development with a CPLD or PAL would've been much easier ... a bread board area was helpful.)

unibus controller rendered

 unibus controller rendered

The QBUS and UNIBUS controller are vanilla, base logic was inspired by DEC BM72 Diode ROM schematic (click to enlarge):

DEC 11 HBMAA E D BM792 Read only memory and MR11 DB Bootstrap Loader Jan75 17 small

There's mainly an address decoder and simple logic to implement QBUS/UNIBUS timing signals for the DATI cycle.
Luckily UNIBUS/QBUS where designed for easy implementation of peripherals boards.

Important: The length of the DATI cycle must be adapted to the diode charge/decharge times, see below.

 Additional circuits required more brain power:

  • timeout for LED display (these can be configered to light for a certain period only)
  • clear LEDs on previous selected matrix boards before next access.
  • switch "anode recovery" levels onto data lines between DATI access cycles.


Physical bits

A single bit in the matrix is made with a combination of diode and switch:

jumpers and diodes


1n4148 jumper single switch single


On the first protoype, I soldered 1024 diodes and 1024 miniature switches manually ... a total of over 5000 solder joints. Then I detected several failures, the worst being these china-switches unreliable: they close when bent slightly left or right.

So the next version used premounted SMD diodes and jumpers ... also encouraged by OCM museum members.

While a bit is more difficult to set than with a switch, the show effect is better:

  • you can omit zero-bits from the matrix, giving a cleaner image
  • you can use different colors, to highlight the use of bits for programs or data

Another topic was "anode recovery": real existing diodes have parasitic capacities, which must be charged and decharged after each level-switch.
In the scope image here the blue channel shows the row select signal going active Low to select a 16 bit word.
The red channel are the effective bit data switched by diode onto bus lines, they are delayed by about 800ns.


The DEC BM792 has a special "anode recovery" circuit to decharge diodes ... I did not understand their logic and inventend an own one, which is less effective.

In the scope trace above you see the red falling edge showing an exponential charge delay, while the sharp raising edge shows my "anode recovery".

But QBUS/UNIBUS cycles can have any timing ... so *please* trim the master/slave timing according to your scope image!


And yes, in a modern EPROM chip, bits and access logic are more compact ...

T3700639 Coloured SEM of surface of an EPROM silicon chip