Why speed it up?

The DL11-W is a serial UNIBUS card manufactured by DEC. The DL11-W is very versatile, but has one drawback: highest baudrate is 9600.
This is fast enough for interactive terminal session.
But if you transmit data over serial line with some kind of protocol, you soon wish it would be faster. Think of applications like

  • Kermit
  • VTserver
  • Disk images transmitted with PDP11GUI
  • DECtape2 emulation with TU58em.

I decided to make a faster DL11-W, when I was sitting two hours before my notebook while reading an 2.5MB RK05 disk image with PDP11GUI. See here the description of a hot PDP-11 session (german page).


Baudrate generation on the DL11-W

The DL11-W schematics are found in document "DL11-W Field Maintenance Print Set (Aug 1977, MP00106)".

On sheet "DL-6" is the baud rate generation:

schematic small

There are two parallel divider circuits:

  • one for 150,300,..9600 baud, formed by E12 and E27.
  • one for 110 baud, formed by E39,E26,E19.

The UART needs a clock of "baudrate * 16", so for 9600 baud a frequency of 153600 must be generated.
153600 is created from a primary clock of 5.0688 MHz by dividing by 33!

This is done by two dividers:

  1. E12.Q3 (divider : 12) with XOR feedback divides / ( 12 - 1) = 11
  2. E27.Q1 (divider :4)   with XOR feedback divides / ( 4 - 1) = 3

The XOR feed back gate generates one additional clock impulse on overflow. So the counter counts "1 clock" faster, and hence is dividing "1 clock less".

This way the "1:12" divider becomes an "1:11", and the "1:4" becomes an "1:3" ... "1:33" is easier than expected.

(Exercise for the reader: verify the divider stages in the "110 baud" branch!)

Speeding up by use of a faster oscillator?

My first try was to replace the 5.0688 MHz oscillator with a faster type. With 20MHz you could get baudrates up to 38400 by merely changing one component.

But this didn't work: the 74xx chips were too slow. 74xx's and 74LSxx's have a delay of 10ns per gate, which should be fast enough for 20MHz. But apparently the XOR feedback in the divider stages produces short pulses, which got lost. So the divider stages were "dividing too much", output frequency was too slow.

There are faster types: 74Sxx has 4ns, 74ASxx has 1.5ns, 74ALSxx has 4ns.  (Source: http://www.fh-sw.de/sw/fachb/et/halbl/stdlogik.htm)

But a 7486 and a 7492 from such a fast family in DIL14 case was too hard to get. I decided to think of another solution instead wasting my time browsing for these parts.