A 2nd version of QProbe is more "Blinkenlighty" now.

qprobe2023 baypanel unpowered

 

A video explains the new board in action:

 

How to get

Business stuff first:

For the moment QProbe2023 can be ordered here ... (and later from some U.S. fellow site).

The base board is €110, the "LED-Plug" is €70, the "Drive-Bay-Panel" is €90.
A kit for BA23 case (3D-print + cables set) is €60 ... or 3D design for free.
If you want it prebuild and tested, add €150 ... (so much to solder!).

Shipping extra.

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Features

The "2023" version has some enhancements:

  • LEDs are now separate from the main PCB.
    This allows either for remote-mounted Blinkenlight units, which are not hidden inside the PDP-11 case.
    Also design of further Light&Switch consoles is much easier.
  • The "drive bay panel" options includes LSI-11 operator switches and Disk-Drive LEDs
  • Drive-LEDs can be connected to QBone or DECs BA23-case-panel.
  • A small plug-on LED panel option replaces the previous light signals.
  • QProbe2023 can also drive these QBUS signals: BRPLY, BHALT, BDCOK and BEVENT.
    This allows implementation of QBUS control registers, as well as implementing the switches for RESTART, HALT and DISABLE LTC.
  • Termination resistors for BDAL<21:18> can be switched off separately.
    This is important for the LSI11/03 M7264 CPU module, which puts some internal microcode signals onto these wires.

 

 

As before, theres a large area dedicated to connect a Logic Anayzer to the QBUS. However, this is considered "optional" ... once your PDP-11 is running, Blinkenlights are most important.

qprobe2023 base

Blinkenlight option 1: "LED-Plug"

This is the dual-LED row from before, plugged onto QProbe via long connectors.

qprobe2023 ledplug active

 

qprobe2023 ledplug back

It is most simple to build, as the LEDs are mounted in a regular way: no complicated 90-degree 3D-print assembly required.

Blinkenlight option 2:"Drive-Bay-Panel"

Retro design

This panel mounts into the 5-25" drive bay of a BA23 case, for example. Here an earlier version without Disk-Drive-LEDs.

qprobe2023 drivebaypanel active

 

qprobe2023 drivebaypanel back

 The design is that of an 1970s PDP-10/12/15 rack header panel:
headerpanel pdp10

So it's definitely not really a "restauration", more a retro-insider-joke: a 1960/70ths 19" panel in a 1980/90th BA23 case!

***

Beside, there are now two switch blocks:

"Operator" are the 3 switches on LSI11/03 resp. 11/23 cases:

pdp11 23 panel

 

Display register

QProbe2023 implements the PDP-11 Display Register at 777570, whose content is visible on UNIBUS Blinkenlight panels, but not implemented on any QBUS machine.
Now it is.

Display Register is write-only, the corresponding Switch-Register on same address is not present.

Display Register is present in all modes, expect 0001. This means QProbe responds properly to a DATO cycle to IO adddress ...7570, actively pulsing BRPLY.

Drive LEDs

 

 

Display Modes

QProbe has 4 switches, which modify behaviour of CPLD logic. They are used to select several types of display or test options. Currently we have:


0000: Regular Display: ADDRESS/DATA are demuxed by SYNC and show on apprioriated LED rows. Short pulsing signals like IRQ or DMA are enlongated so they are visibile to the human eye.

0001: "Fully passive". QBUS signals are put onto LEDs unprocessed. ADDRESS is BDAL, DATA not used. 
Display Register is NOT implemented in this mode. Useful for static checkout of backplanes

0010: "Test Mode", LED test. Like 0001, but DATA shows a copy of ADDRESS. Used for LED test after assembly.

0011: Same as 0000, but detection of CPU HALT and signal generation on pin LA[0]. CPU stop is recognized when microcode ODT access UART at 777560 without interwoven opcode fetches.

0100: Show "Display Register" content on DATA LEDs.


Other ideas for "Mode" include:

  • A pulsing bargraph showing IRQ/DMA load.
  • Force/suppress longer display of IRQ and DMA pulses.
  • Route some QProbe LA signal inputs to some LEDs. This way other signals from the PDP-11 guts may get visible.eas, but limited by my Verilog capabilities ...