PDP11GUI Machine Description File
One major feature of PDP11GUI is the display of symbolic information for memory addresses. This saves you from spending lot of time for just scanning through pages of printed documentation. (See the description of the Bitfields window too).
The register information is kept in the “machine description file”. This is a text file in Windows “.INI” file format. The file is loaded over the “File” menu, it’s name can also be given on PDP11GUI’s command line. Its default location is in the users’s “Documents and Settings” directory. After loading, the macro preprocessor M4 is run over the file .. here you see why).
In this file you define
- what devices are plugged into your backplane
- which register addresses occupy those devices
- what names have those registers in DEC’s documentation,
- what function have those registers
Most registers are broken up into several bit fields. Symbolic information can be given for those bit fields too.
The machine definition file reflects the physical configuration of a certain target machine. If you have a physical PDP-11 connected to PDP11GUI, it must reflect the hardware you have plugged into your backplane.
If you have SimH connected, it’s related to the SimH devices configuration you are running.
See as example the part of my machine description file describing the common PDP-11 CPU registers:
; temporarily disable an entry with "Enabled=0" or "Enabled=false".
PSW =177776;"Processor Status Word";Bits.CPU.PSW
PIRQ =177772;"Program Interrupt Request";Bits.CPU.PIRQ
SP=177706;"stack pointer = R6"
PC=177707;"program counter = R7"
R16=177716;"Supervisor mode stack pointer"
R17=177717;"Kernel mode stack pointer"
Current Mode=15:14;"Current processor mode. 0=kernel,1=supervisor,2=illegal,3=user mode"
Previous Mode=13:12;"Processor mode prior to last trap, irq oder PSW loading"
CIS Instruction Suspension=8;"1, when a CIS instruction is entered and completed"
Priority=7:5;"Current level of processor priority"
T=4;"Trap: when 1, trap to 14. Debugging."
PIRQ Level=15:9;"PIR7-PIR1 - interrupt request of given priority level"
PIA-Hi=7:5;"Program interrupt active, MSB"
PIA-Lo=3:1;"Program interrupt active, LSB"
Data Transfer=15;"Monitors DATA TRAN line. 0 = UNIBUS transfer"
C1=14;"1 when UNIBUS control signal BS C1 is asserted"
Cache Restart=13;"1, when cache has restartet processor clock"
KTE=12;"1, when memory management error has occured"
Bus Error=11;"1, when access to non existing memory, or UNIBUS 20us timeout"
Parity Error=10;"1, when memory parity error"
AC LO=9;"UNIBUS AC LO asserted."
DC LO=8;"UNIBUS DC LO asserted."
Illegal Halt=7;"Halt instruction in user or supervisor mode"
Odd Address Error=6;"Program attempted a word reference on an odd address"
Memory Time-Out=5;"Read from non-existant memory. Does not include UNIBUS addresses"
UNIBUS Time-Out=4;"No response from UNIBUS within 20 µs"
Processor Initialize=3;"This bit monitors the processor initialize signal"
Stack Overflow=2;"Kernel hardware stack is less than octal 400"
Interrupt=1;"PAX interrupt line is asserted"
CIM Power Failure=0;"DC power to the machine has exceeded voltage tolerance limit for more than 1.5 µs"
- The line “[CPU]” indicates a new device (= register group) definition. A new register window for the device “CPU” can now be selected from the “memory” menu.
- The line “Info=...” explains the device, this is shown as info in the register window.
- The line “Enabled=1” is obsolete. However, if you temporarily want to disable a device definition, include the line “Enabled=0” or “Enabled=false”
- the following lines until the next “[...]” header are register definitions.
If you have several instances of the same device on different addresses (for example, if you have plugged in two identical disk controllers), you must repeat the whole device definition with different register addresses.
Register definitions have the form:
register name=address[:address];information[;bit field definition]
- register name
is the name DEC gave the register. It should be short, and unique within the device. Example: “PSW”
address is the physical octal address of the register. It is always given as 16 bit address even for 18 bit or 22 bit machines! This has two reasons:
- It makes the definitions movable between different PDP-11 models.
- The human eye is not puzzled by too many ‘7’-digits.
Since all peripherals registers are located in “IO-page”, the upper 8 kBytes of the 16/18/22 bit address space, the register address must be in the range 160000 ... 177776
The expression “address:address” is interpreted as address range, intended as a short description for ROM or RAM areas. and
is the same for each address in the range, but addresses get “[index]” suffixes appended automatically to their names.
information is a long text explaining the registers use.
It will contain white space and must be surrounded by “..”
Example “Processor Status Word”
bit field definition is an optional section header of the form “[Bits....]”. It points, to the bit field defintions for this register.
Multiple registers can reference the same bitfield definition
A bit field definition begins with an INI- file section header of form “[Bits.bitfield definition name
Every line following the header contains one bit field definition of the form
bitgroup= from_bit[:to_bit ];information .
bitgroup is the bit fields name, as given in the DEC documenation. It must be unique inside the bit field definitions.
Example: “Current Mode”
from_bit : to_bit indicate the bits range the bit field occupies. Bits are counted decimal: from 15 down to 0..
information is a long description of the bit field. If it contains white space character, it must be surrounded with “...” quotes.
Example: “Current processor mode. 0=kernel,1=supervisor,2=illegal,3=user mode"”