PDP11GUI Machine Description File

Parent Category: Tools Category: PDP11GUI Written by Administrator

 One major feature of PDP11GUI is the display of symbolic information for memory addresses. This saves you from spending lot of time for just scanning through pages of printed documentation. (See the description of the Bitfields window too).

The register information is kept in the “machine description file”. This is a text file in Windows “.INI” file format. The file is loaded over the “File” menu, it’s name can also be given on PDP11GUI’s command line. Its default location is in the users’s “Documents and Settings” directory. After loading, the macro preprocessor M4 is run over the file .. here you see why).

In this file you define

Most registers are broken up into several bit fields. Symbolic information can be given for those bit fields too.

The machine definition file reflects the physical configuration of a certain target machine. If you have a physical PDP-11 connected to PDP11GUI, it must reflect the hardware you have plugged into your backplane.
If you have SimH connected, it’s related to the SimH devices configuration you are running.

See as example the part of my machine description file describing the common PDP-11 CPU registers:

[CPU]
Info=CPU Register
; temporarily disable an entry with "Enabled=0" or "Enabled=false".
Enabled=1
PSW      =177776;"Processor Status Word";Bits.CPU.PSW
PIRQ     =177772;"Program Interrupt Request";Bits.CPU.PIRQ
CPU Error=177766;;Bits.CPU.Error
R0=177700
R1=177701
R2=177702
R3=177703
R4=177704
R5=177705
SP=177706;"stack pointer = R6"
PC=177707;"program counter = R7"
R10=177710;"temporary storage"
;R11=177711
R12=177712;"temporary storage"
R13=177713;"temporary storage"
R14=177714;"temporary storage"
R15=177715;"temporary storage"
R16=177716;"Supervisor mode stack pointer"
R17=177717;"Kernel mode stack pointer"

[Bits.CPU.PSW]
Current Mode=15:14;"Current processor mode. 0=kernel,1=supervisor,2=illegal,3=user mode"
Previous Mode=13:12;"Processor mode prior to last trap, irq oder PSW loading"
CIS Instruction Suspension=8;"1, when a CIS instruction is entered and completed"
Priority=7:5;"Current level of processor priority"
T=4;"Trap: when 1, trap to 14. Debugging."
N=3;Negative
Z=2;Zero
V=1;Overflow
C=0;Carry

[Bits.CPU.PIRQ]
PIRQ Level=15:9;"PIR7-PIR1 - interrupt request of given priority level"
PIA-Hi=7:5;"Program interrupt active, MSB"
PIA-Lo=3:1;"Program interrupt active, LSB"

[Bits.CPU.Error]
Data Transfer=15;"Monitors DATA TRAN line. 0 = UNIBUS transfer"
C1=14;"1 when UNIBUS control signal BS C1 is asserted"
Cache Restart=13;"1, when cache has restartet processor clock"
KTE=12;"1, when memory management error has occured"
Bus Error=11;"1, when access to non existing memory, or UNIBUS 20us timeout"
Parity Error=10;"1, when memory parity error"
AC LO=9;"UNIBUS AC LO asserted."
DC LO=8;"UNIBUS DC LO asserted."
Illegal Halt=7;"Halt instruction in user or supervisor mode"
Odd Address Error=6;"Program attempted a word reference on an odd address"
Memory Time-Out=5;"Read from non-existant memory. Does not include UNIBUS addresses"
UNIBUS Time-Out=4;"No response from UNIBUS within 20 µs"
Processor Initialize=3;"This bit monitors the processor initialize signal"
Stack Overflow=2;"Kernel hardware stack is less than octal 400"
Interrupt=1;"PAX interrupt line is asserted"
CIM Power Failure=0;"DC power to the machine has exceeded voltage tolerance limit for more than 1.5 µs"
 

Device definitions:

If you have several instances of the same device on different addresses (for example, if you have plugged in two identical disk controllers), you must repeat the whole device definition with different register addresses.

Register definitions:

Register definitions have the form:

register name=address[:address];information[;bit field definition]

 

Bitfield definitions:

A bit field definition begins with an INI- file section header of form “[Bits.bitfield definition name” ]. If a header begins with “Bits.” it is always interpreted as bit field definition and not as device definition. bitfield definition name must be unique inside the whole machine definition file, so it has mostly the form “devicename.bit field name”.

Every line following the header contains one bit field definition of the form

bitgroup=from_bit[:to_bit];information.