If we enlarge the view to 1 microsecond, the operation of the micro machine comes into view.
Signals
MSYN. SSYN: UNIBUS handshake signals between CPU and ROM
PROCCLK: clock of micro machine
MPC: 9 bit micro program counter, which addresses the micro instructions.
What you see
The screen shot shows the micro steps following the fetch of the first instruction after BOOT. Marker "D" is at the same position as in the previous zoom level.
You can distinguish four pulses of clock signal PROCCLK. This is the basic CPU clock for the micro program counter. Modern micro processors have a clock corresponding to the instruction cycle, but the PDP-11 has a clock signal driving the micro machine. The pulses are some 200 nanosconds apart and 30ns width.
The micro program counter changes a lot, but on the falling edge of PROC CLK it is always stable. At this point the next micro instruction is fetched and executed, after that the MPC changes again as result of address re-calculation.
The micro steps in the screen shot are these:
| Marker | MPC (hex) |
MPC (octal) |
DEC original |
Info |
| D | 0x00E | 016 |
Fetch next instr,
|
SSYN Low->High |
| C | 0x00D | 015 | Increment PC, Micro branch on instruction |
R7 is increment by 2 |
| E | 0x020 | 040 | SOP |
Data "5003" is decoded. The MPC is cleared and overlaid with data from the instruction decoder ROMs. The "CLR" instruction needs only one micro step. |
| F | 0x000 | 000 | Service Intr/Traps, store vector |
After every instruction, the loop returns to MPC 000. Here status bits are scanned for errors or interrupts. |
| G | 0x00E | 016 | Fetch next instr, load into IR |
Again the next instruction is fetched from UNIBUS, MSYN will go low as soon SSYN goes low and the UNIBUS is released (the ROM still has SSYN High!) |
See the start of the micro code flow charts in the PDP-11/34 field maintenance print set:
Some remarks
Normally the cycles begins at MPC = 000 (trap service). But the instruction fetch at MPC=016 lasts very long, and PROC CLOCK is stopped until SSYN goes High again. Therefore we show here the steps between two fetches, from MPC=016 until MPC is 016 again.
At MPC = 000, the existence of traps, interrupts or error signals is checked. On any condition a branch to special micro code is executed. (Perhaps you learned the distinction between fast "Interrupt driven I/O" and slow "polled I/O" ? Well, here you see that on the micro code level, interrupts are merely polled by the micro code loop.)
At MPC =015, the program counter in R7 is incremented by 2. We will dive into this on the next page!
Between the PROCCLK pulses, there's a lot of changing on the MPC lines. Normally the next MPC is given by the current micro word (each micro instruction contains an implicit "GOTO"). But as signals loop through the data path circuits, MPC lines may be changed to execute "Branch On Micro Tests", so MPC has a lot of noise on it.