Well, lets go deeeep into details: how is DIGI-COMP I actually working ?

When you look at DIGI-COMP at high detail level, you see it has quite a sophisticated design. Lots of mechanical problems were solved with cheapest means, and the resulting product is end-user save. This is outstanding engineering!

I'll not reproduce their excellent manual here, just light their mechanic in modern terms.

As said before, DIGI-COMP I implements a Medvedev State Machine, consisting of flip flops and a combinatory logic block.

On DIGICOMP, the trasnfer of funmctiom delta results into flip-flops is done via RESET and SET pulses.

inA |
inB | inC |
outA |
outB | outC |
outA reset | outA set | outB reset | outB set | outC reset | outC set | ||

0 | 0 | 0 | => | 1 | 0 | 0 | => | x | |||||

1 | 0 | 0 | => | 0 | 1 | 0 | => | x | x | ||||

0 | 1 | 0 | => | 1 | 1 | 0 | => | x | |||||

1 | 1 | 0 | => | 0 | 0 | 1 | => | x | x | x | |||

0 | 0 | 1 | => | 1 | 0 | 1 | => | x | |||||

1 | 0 | 1 | => | 0 | 1 | 1 | => | x | x | ||||

0 | 1 | 1 | => | 1 | 1 | 1 | => | x | |||||

1 | 1 | 1 | => | 0 | 0 | 0 | => | x | x | x |

Speaking in terms of modern electronic: there is no clocked DATA input and neither asynchronous set/reset, but separate synchronous SET and RESET signals are clocked into the flip-flops. (So the flip flops are *not* JK-style as in the 7474 TTL chip).

Combinatory logic functions can be implemented as primary AND terms finally ORed together. That is called "Sum Of Products" in the Canonical Normal Form (CNF).

The idea behind is: You can write any logical function as truth table. Example for an arbitrary nonsense function:

A |
B |
C | result Q |
Row selecting AND-Terms for Q=1 |

0 | 0 | 0 | 0 | |

0 | 0 | 1 | 1 | NOT A AND NOT B AND C |

0 | 1 | 0 | 0 | |

0 | 1 | 1 | 1 | NOT A AND B AND C |

1 | 0 | 0 | 1 | A AND NOT B AND NOT C |

1 | 0 | 1 | 0 | |

1 | 1 | 0 | 0 | |

1 | 1 | 1 | 1 | A AND B AND C |

To calculate the equivalent gate-network, you first pick out with individual AND terms all the A,B,C combinations which yield Q=1 .

In a 2nd stage you build the OR of all theses ANDs, so Q is 1 when any listed A,B,C combination comes true.

This results in impressive bandworm formulas like

Q(A,B,C) = (NOT A AND NOT B AND C) OR (NOT A and B and C) OR (A AND NOT B AND NOT C) OR (A AND B AND C)

but the resulting logic circuit is just a 2-stage cascade of AND and OR gates.

The internal structure of Programmable logic arrays is the same, and also DIGI-COMP works this way.

The difference with DIGI-COMP is that the "Sum Of Products" only calculates the SET signal. Also all conditions yielding Q=0 must be decoded to generate the RESET signal.

To implemement all possible logic functions for 3 bits, DIGI-COMP should have 2^{3} = eight AND terms (logic rods). But there only 6, and these are hard-wired as 3 SET and 3 RESET condtions. It needs to be investigated how much this hampers possible applications.

After theory lets go through all the plastic stuff now.

To show the Logic and Clock mechanic, we concentrate on just one rule from the "Binary Counter" example.

This logic rule is: "Flip-flop B must be set, when in the step before Flip-flop A=1 AND Flip-flop B=0".

See the desired counting sequence:

# | Count sequence on A,B,C | Result of "A=1 AND B=0" | B operation on clock |

1 | 1,1,1 | false | |

2 | 0,0,0 | false | |

3 | 1,0,0 | true | set to "1" |

4 | 0,1,0 |
false | |

5 | 1,1,0 | false | |

6 | 0,0,1 | false | |

7 | 1,0,1 | true | set to "1" |

8 | 0,1,1 |
false | |

9 | 1,1,1 | false |

The AND term of this rule is programmed on the front side:

On the backside, LOGIC ROD "Set 4" is coupled via top sliders to CLOCK ROD "Set 4", and connected to Flip-flop "B" via a CLOCK PEG:

Below are two videos showing LOGIC and CLOCK RODs in action:

Well, after seeing these exciting movies, you surely need some slow down.

So here comes this mandatory boring part of every technical article: the "Reference chapter".

Due to the feedback loop, theres a circular Signal flow through the DIGI-COMP construction.

FLIP FLOP state -> READOUT PEGS -> READOUT TUBES -> "AND" by LOGIC RODs -> TOP SLIDERS -> CLOCK RODs ("in-out" movement) -> CLOCK PLATEs -> CLOCK RODs ("left-right" movement) -> "OR" by CLOCK TUBES -> CLOCK PEGS -> FLIP FLOP state.

There are 3 FLIP FLOPs, implemented as sliders. Here only top FLIP FLOP "A" is highlighted.

A FLIP FLOP has a numeric indicator, showing "0" or "1".

And a FLIP FLOP has 3 pairs of pegs, these are the "outputs". In each pair there is a "T" peg for the FLIP FLOP state, and a "F" peg for the inverted state.

So a flip flop can drive 3 different signals in any polarity.

Tubes program which FLIP FLOP outputs are to be ANDed onto the logic rods. Inverted or non-inverted outputs pegs can be used.

TUBEs on PEGs |
Value for LOGIC ROD AND term |

"T" | FALSE (inactive) when flip flop = 0 |

"F" | FALSE (inactive) when flip flop = 1 |

"T"+"F" | Always FALSE, LOGIC rod always inactive |

none | Logic rod not influenced by this FLIP FLOP |

LOGIC RODs calculate the **mechanical AND** of up to 3 FLIP FLOPs. Depending on the LOGIC TUBEs, inverted or non-inverted FLIP FLOP states are ANDed in.

A FLIP FLOP output with set PEG is interpreted as FALSE and prohibits the LOGIC ROD from being pulsed toward the DIGI-COMP body. So the top slider is only moved toward the CLOCK side if no flip-flop has a PEG moved before the ROD.

Top sliders connect AND logic on the front with OR and CLOCK logic on the back side.

The SLIDERS have quite a complex form, as they must execute an "in-out" movement and later fix the CLOCK RODs in their "left-right" operation.

There are special OR sliders, which move two CLOCK RODs if one LOGIC rod is activated. I dont't show these here.

There are 3 pairs of CLOCK RODs, 3 for SET and 3 for RESET signals. CLOCK RODs have two functions:

- Activated clock rods are pushed away from DIGI-COMP by activated LOGIC RODs via TOP SLIDERS ("in-out" movement). Rods slip into narrow cut-outs in the clock plates then.
- On clock plate movement these narrow clock cut-outs move CLOCK RODs "left-right" and against CLOCK PEGs.

The lower clock plate pushes activated SET rods against SET CLOCK TUBES. It is driven by the manual clock handle.

The upper clock plate runs reversed to the lower SET plate. It is driven by the SET PLATE via a motion-reversing wire crank.

If a CLOCK ROD is activated, it slips into a special cut-out on the CLOCK plate, the clock plate catches it and moves it against one of the CLOCK TUBEs (if installed).

So the logical "in-out" movement of CLOCK RODs is converted into a "left-right" movement to change the FLIP FLOP state.

This done by several tricky cut-outs. The lower SET CLOCK plate has a "T"-style cut-out to catch the SET CLOCK ROD, and a large cut-out to bypass the ignored RESET ROD. Equally the upper RESET CLOCK plate has a "T"-style cut-out to catch the RESET CLOCK ROD, and bypasses the SET ROD.

Each FLIPFLOP has 3 pairs of CLOCK PEGS were CLOCK TUBEs can be installed.Activated CLOCK RODs move against these TUBEs , allowing 3 different SET or RESET CLOCK-ROD conditions to move the flip-flop. These conditions are **logical OR**ed: the flip flop is moved if at least one of the SET or RESET TUBEs is installed and the CLOCK ROD gets activated.

If both SET and RESET CLOCK ROD is activated at the same time and BOTH a SET and RESET TUBE are installed, this means the flip flop has to SET and RESET at the same time. We have programmed a contradictionary signal short cut then, resulting in mechanical jam.

If a flip flop has neither SET nor RESET TUBE installed, that FLIP FLOP is never changed by CLOCK. It then acts a pure INPUT parameter, see Medvedev State Machine above.